Advances in manufacturing technology have enabled larger and denser circuits to be placed on single semi-conductor integrated circuits. This is especially the case when the circuits are realized as regular or cellular structures, for example Random Access Memory. A major problem associated with high density device is that of testing. In order to maintain higher reliability, device test procedures need to provide good coverage of possible faults that occur in the integrated circuit.
One technique for providing testing of an integrated circuit is the so-called SIST architecture (signal integrity self-test architecture). The purpose of SIST architecture is to allow real time monitoring of important parameters which characterize the electrical behaviour of the integrated circuit. For example, monitors can be provided to detect cross talk, supply noise, substrate noise, temperature, switching activity, clock duty cycle etc. An SIST architecture has the advantage that testing can be performed before use during a test and debug process, and also during use (on-line).
FIG. 1 of the accompanying drawings is a block diagram illustrating an integrated circuit including previously considered Signal Integrity Self Test (SIST) architecture. The integrated circuit 100 comprises a number of functional cores or modules 200. These modules may perform analogue, digital or memory functions. For simplicity, it has been assumed that all cores are the same size. It will be readily appreciated that such techniques are not limited to an integrated circuit having cores of the same size. In addition, the normal interconnections and buses, which perform communication controls between the different functional cores, have been omitted from the diagram for the sake of clarity.
The integrated circuit 100 includes a monitor control block 400 which communicates with a number of monitors (not shown in FIG. 1) using a monitor selection bus 600. A reference and compare circuit 800 outputs a self-test signal from an output 1000 in dependence upon received signals from the monitors. The monitors supply monitor output signals via a bus structure 1200. The monitors are intended to be designed as standard cells, so that they can be located anywhere within each standard-cell block.
FIG. 2 of the accompanying drawings illustrates a functional core 200 from the integrated circuit of FIG. 1. The core 200 includes a plurality of monitors 1600 connected to a decoder 1400 and to the bus structure 1200. In FIG. 2, the functional blocks relating to the function of the core have been omitted for the sake of clarity. FIG. 2 illustrates an exemplary core having four monitors 1600. It will be readily appreciated that the core can be provided with any number of monitors in dependence upon the parameters to be measured. As mentioned above, different sensors are used to monitor different phenomena: cross talk, supply noise, substrate noise, temperature, switching activity, clock duty-cycle, etc.
The SIST architecture (FIG. 1) allows access to each individual monitor in a core using the monitor selection bus 600, which is controlled by the monitor control block 400. The monitor control block 400 includes a memory, which contains specific codes through which a certain monitor in a specific core can be selected. The output of the selected monitor is usually converted to a DC value or into a differential signal, which is then connected to the bus structure 1200. This bus structure 1200 may either be connected directly to a bondpad 1000 of the integrated circuit, or, as shown, it may be connected to the reference and compare circuit 800. In one particular example, the reference and compare circuit 800 operates to determine whether the output signal from the monitor is within a certain allowed range. The reference and compare block 800 may contain reference values for each kind of monitor.
The monitor control block 400 can be placed on the integrated circuit, but can also be an external controller, for example a software program or an analysis tool. In all cases, it is necessary to provide a means to communicate between all monitors 1600 and the monitor control block 400.
The continued reduction of feature sizes in deep sub micron CMOS has led to integrity problems in advanced digital CMOS circuits.
One of the integrity problems is associated with the power supply, the ground return path and the substrate potential. Voltage drops can already be detected in the layout phase. However, temporary dips on power supplies, or bounces on ground and substrate have a very local character, and are difficult to predict or determine in a device under test. Therefore, “signal integrity self test” (SIST) monitors aim at measuring and reporting these temporary voltage fluctuations.
Measuring voltage excursions (such as dips or bounces) is a very common problem and existing solutions are available. In the case of a digital CMOS integrated circuit, however, some constraints limit the possibilities for proper measurement:
Feeding additional lines to the points of interest and measuring on the outside of the chip, is not possible: because the wires would pick up signals that do not exist at the measurement points and additional external pins are needed.
Building a full Analog to Digital converter to provide a digital signal representing the voltage measurement would cost too much IC area and post additional power constraints on the circuit.
It is, therefore, an object of the present invention to provide an improved voltage measurement apparatus for such integrated circuits.